1. Field of the Invention
The present invention relates to analog to digital converters ADC, and more particularly, to analog to digital converters utilizing track-and-hold amplifiers for high speed operation.
2. Related Art
A subranging analog to digital converter (ADC) architecture is suitable for implementing high-performance ADC's (i.e. high speed, low power, low area, high resolution). FIG. 1 shows the generic two-step subranging architecture, comprising a reference ladder 104, a coarse ADC 102, a switching matrix 103, a fine ADC 105, coarse comparators (latches) 107, fine comparators (latches) 108 and an encoder 106. In most cases, a track-and-hold 101 is used in front of the ADC. In this architecture, an input voltage is first quantized by the coarse ADC 102. The coarse ADC 102 and the coarse comparators 107 compare the input voltage against all the reference voltages, or against a subset of the reference voltages that is uniformly distributed across the whole range of reference voltages. Based on a coarse quantization, the switching matrix 103 connects the fine ADC 105 and the fine comparators 108 to a subset of the reference voltages (called a “subrange”) that is centered around the input signal voltage. The coarse and fine comparators 107, 108 latch the outputs of the coarse and fine ADC's 102, 105 prior to inputting them to the encoder 106.
High-speed high-resolution ADC's usually use a track-and-hold (T/H) or a sample-and-hold (S/H) preceding the ADC. The main distinction between a S/H and a T/H is that a S/H holds the sampled input signal for (almost) a full clock period, whereas a T/H holds the sampled input signal for (almost) half a clock period.
In general, a S/H requires more area and power than a T/H to obtain the same performance. However, the disadvantage of a T/H is that the sampled input signal is available to the ADC for only half a clock period.
Other subranging ADC's are known that can use a T/H instead of a S/H. However, the timing proposed in conventional art has important disadvantages.
Typically, both the coarse and fine ADC amplifiers reset to the T/H output voltage. This leaves much less time available for the coarse ADC amplifiers to amplify the signals and the coarse comparators to decide on a voltage to latch. This will impact a maximum sampling speed Fsample that the ADC can run at.
Some ADC's use a T/H, where the same physical circuits are used for performing both the coarse and the fine quantization. This leaves only ¼ of a clock cycle available for performing the coarse quantization, or two time-interleaved sub-ADC's have to be used. This impacts either maximum possible operating speed, or doubles required area and power.
Thus, one of the bottlenecks in subranging ADC's is the limited amount of time available for performing the coarse quantization. Several different timing methods for subranging ADC's are known for optimizing this bottleneck. Unfortunately, most of these solutions require the use of a S/H, or use time-interleaved ADC's. This disadvantageously affects the required power and area.